Home » Computer Architecture » 8051 Microcontroller
Que: 61 When any interrupt is enabled, then where does the pointer moves immediately after this interrupt has occurred? a. to the next instruction which is to be executed b. to the first instruction of ISR c. to the first location of the memory called the interrupt vector table d. to the end of the program
Show Answer (c). to the first location of the memory called the interrupt vector table
Que: 62 What are the contents of the IE register, when the interrupt of the memory location 0x00 is caused? a. 0xFFH b. 0x00H c. 0x10H d. 0xF0H
Que: 63 After RETI instruction is executed then the pointer will move to which location in the program? a. next interrupt of the interrupt vector table b. next instruction of the program after the IE instruction c. next instruction after the RETI in the memory d. none of the mentioned
Show Answer (b). next instruction of the program after the IE instruction
Que: 64 Which pin of the external hardware is said to exhibit INT0 interrupt? a. pin no 10 b. pin no 11 c. pin no 12 d. pin no 13
Que: 65 Which bit of the IE register is used to enable TxD/RxD interrupt? a. IE.D5 b. IE.D2 c. IE.D3 d. IE.D4
Que: 66 Which of the following combination is the best to enable the external hardware interrupt 0 of the IE register (assuming initially all bits of the IE register are zero)? a. EX0=1 b. EA=1 c. any of the mentioned d. both of the mentioned
Show Answer (d). both of the mentioned
Que: 67 Why normally LJMP instructions are the topmost lines of the ISR? a. so as to jump to some other location where there is a wider space of memory available to write the codes b. so as to avoid overwriting of other interrupt instructions c. both of the mentioned d. none of the mentioned
Show Answer (c). both of the mentioned
Que: 68 Which register is used to make the pulse a level or a edge triggered pulse? a. TCON b. IE c. IPR d. SCON
Que: 69 What is the disadvantage of a level triggered pulse? a. a constant pulse is to be maintained for a greater span of time b. difficult to analyse its effects c. it is difficult to produce d. another interrupt may be caused, if the signal is still low before the completion of the last instruction
Show Answer (d). another interrupt may be caused, if the signal is still low before the completion of the last instruction
Que: 70 What is the correct order of priority that is set after a controller gets reset? a. TxD/RxD > T1 > T0 >EX1 > EX0 b. TxD/RxD < T1 < T0 c. EX0 > T0 > EX1 >T1> TxD/RxD d. EX0 < T0 < EX1 < T1 < TxD/RxD
Show Answer (c). EX0 > T0 > EX1 >T1> TxD/RxD
Que: 71 How many rows and columns are present in a 16*2 alphanumeric LCD? a. rows=2, columns=32 b. rows=16, columns=2 c. rows=16, columns=16 d. rows=2, columns=16
Que: 72 How many data lines are there in a 16*2 alphanumeric LCD? a. 16 b. 8 c. 1 d. 0