Que: 242. Timer_B includes
|
| a. sampling inputs |
| b. driving outputs |
| c. both of the mentioned |
| d. none of the mentioned |
Que: 243. The watchdog counts up and resets the MSP430 when it reaches the limit?
|
| a. TRUE |
| b. FALSE |
| c. can’t be said |
| d. depends on the conditions |
Que: 244. Which of the following is correct about WDTCTL?
|
| a. it is a 16 bit register |
| b. it is guided against accidental writes that require a password |
| c. a reset will occur if a value with an incorrect password is written to WDTCTL |
| d. all of the mentioned |
(d). all of the mentioned
Que: 245. WDTNMI is found in the
|
| a. higher byte of WDTCTL |
| b. lower byte of WDTCTL |
| c. its first four bits |
| d. its last four bits |
(b). lower byte of WDTCTL
Que: 246. Which of the following bits reads 0 under normal conditions but goes 1 when it wants to initiate some action?
|
| a. WDTNMI |
| b. WDTHOLD |
| c. WDTTMSEL |
| d. WDTCNTCL |
Que: 247. WDTISx bits control the
|
| a. period of the clock |
| b. act as “Nonmaskable Interrupts” |
| c. stop the watchdog timer |
| d. start the watchdog timer |
Que: 248. The process of setting the WDTCNTCL bit in WDTCTL is through
|
| a. petting |
| b. feeding |
| c. kicking |
| d. all of the mentioned |
(d). all of the mentioned
Que: 249. What is the function of this instruction “WDTCTL = WDTPW | WDTCONFIG”, where **#define WDTCONFIG (WDTCNTCL|WDTSSEL)**
|
| a. it sets the watchdog timer |
| b. it configures and clears the watchdog timer |
| c. it stops the watchdog timer |
| d. it configures and sets the watchdog timer |
(b). it configures and clears the watchdog timer
Que: 250. Is this instruction correct?WDTCTL_bit.WDTCNTCL = 1;
|
| a. yes |
| b. no |
| c. can’t be said |
| d. depends on the conditions |
Que: 251. Setting the WDTTMSEL bit of the WDTCTL register makes the watchdog timer act as
|
| a. interrupt |
| b. communication device |
| c. converter |
| d. interval timer |