Que: 272. Their is double buffering in the immediate mode?
|
| a. TRUE |
| b. FALSE |
| c. can’t be said |
| d. depends on the conditions |
Que: 273. Double buffering protects channel 0.
|
| a. as it acts as the limit in the Up and up/down modes |
| b. it doesnot actually protect it |
| c. as it does not accepts the inputs |
| d. none of the mentioned |
(a). as it acts as the limit in the Up and up/down modes
Que: 274. Timer_B has
|
| a. three serial communication ports |
| b. seven LCD driver |
| c. seven compare/capture channels |
| d. three LED driver ports |
(c). seven compare/capture channels
Que: 275. The capture/compare registers TBCCRn are double-buffered, when used for compare events?
|
| a. TRUE |
| b. FALSE |
| c. can’t be said |
| d. depends on the conditions |
Que: 276. The length of TBR can be programmed to be
|
| a. 8 bits |
| b. 12 bits |
| c. 16 bits |
| d. all of the mentioned |
(d). all of the mentioned
Que: 277. TBOUTH can pin can be used to
|
| a. values are moved from one place to another |
| b. the length of the number of bits is selected by this register |
| c. it can be used to put all the outputs of the Timer_B register in the high impedance state |
| d. it can be used for outputting the input values of the timers |
(c). it can be used to put all the outputs of the Timer_B register in the high impedance state
Que: 278. TBCLn provided in each channel is actually
|
| a. a comparator |
| b. compare latch |
| c. controller |
| d. control logic |
Que: 279. When TBR counts to zero
|
| a. TBCLn is updated from TBCCRn |
| b. CLLDx is updated to TBCCTLn |
| c. CLLDx is updated to TBCCRn |
| d. TBCLn is updated to CLLDx |
(a). TBCLn is updated from TBCCRn
Que: 280. Which of the following is the analog to digital converter that is present in the MSP430 based processors?
|
| a. comparator |
| b. successive approximation ADC |
| c. sigma delta ADC |
| d. all of the mentioned |
(d). all of the mentioned
Que: 281. Higher resolution along with the slow speed is given by which ADC module?
|
| a. comparator |
| b. successive approximation ADC |
| c. sigma delta ADC |
| d. all of the mentioned |