Que: 332. Writing on the trailing edge of the clock pulse and reading on the leading edge of the clock pulse is done when
|
| a. CPHA is set |
| b. CPHA is reset |
| c. CPOL is set |
| d. CPOL is reset |
Que: 333. When CPOL=1 then,
|
| a. clock idles high between transfers |
| b. clock idles low between transfers |
| c. bit idles high between transfers |
| d. bit ideals low between transfers |
(a). clock idles high between transfers
Que: 334. Is CPKH and CPOL the same
|
| a. yes |
| b. no |
| c. can’t be said |
| d. depends on the conditions |
Que: 335. SPI with the USI can be selected by
|
| a. setting the USII2C bit in the register USICTL1 |
| b. clearing the USII2C bit in the register USICTL1 |
| c. setting the USIPE5–7 bits in USICTL0 |
| d. clearing the USIPE5–7 bits in USICTL0 |
(b). clearing the USII2C bit in the register USICTL1
Que: 336. SCLK, SDO, and SDI are found___________on F20x3.
|
| a. P1.0-2 |
| b. P1.2-4 |
| c. P1.4-6 |
| d. P1.5-7 |
Que: 337. Transmission and reception are made at a time in SPI?
|
| a. TRUE |
| b. FALSE |
| c. can’t be said |
| d. depends on the conditions |
Que: 338. When the buffer is________ the low power mode is__________
|
| a. empty, reset |
| b. having one byte, reset |
| c. full, reset |
| d. empty, two |
Que: 339. Falling edge of the SS pin denotes
|
| a. end of the transfer |
| b. starts a new transfer |
| c. selects a new master |
| d. none of the mentioned |
(b). starts a new transfer
Que: 340. The I2C bus uses which of the following lines
|
| a. CLK |
| b. MISO |
| c. SDA |
| d. All of the mentioned |
Que: 341. I2C is faster means of data transfer than SPI?
|
| a. yes |
| b. no |
| c. depends on the conditions |
| d. can’t be said |